Volatile memories, such as static RAM latches are well known in the art. They are characterized by their ability to store and read out very quickly the data content stored therein. However, a drawback of volatile memory cell, such as a SRAM, is that the data content is lost once power is turned off.
Non-volatile memory cells, such as those using a floating gate to store electrical charges thereon, is also well known in the art. Their advantage is that the data content is stored even if power is turned off. However, the storing of even a single bit of information in a non-volatile memory cell is much slower than the storing of the bit information in a volatile memory cell.
Heretofore, the use of a combination of an SRAM with non-volatile memory cells is also well known in the art. Referring to FIG. 1, there is shown one embodiment of a combination circuit 10. The circuit 10 comprises a conventional SRAM 20. The SRAM 20 is characterized by a pair of cross-coupled PMOS transistors 22 and 24, and a pair of cross-coupled NMOS transistors 26 and 28. At a first node 30, the input/output signal to and from the SRAM 20 can be provided. At the second node 32, the inverse of the signal provided at the first node 30 can be provided to or from the SRAM 20. Thus, as shown in FIG. 1, conventionally, the signal line BL is shown as being supplied to the first node 30 and its inverse BL is supplied to the second node 32. Each of the signals BL and BL are supplied through respective switching transistors 34 and 36 whose gates are connected to the signal EERCL and which when activated serves to pass through the signal BL or BL to or from the SRAM 20.
The non-volatile memory cell section of the circuit 10 comprises a pair of split gate floating gate memory cells 40 and 42 of the type that is described in U.S. Pat. Nos. 5,029,130 and 5,572,054, whose disclosures are incorporated herein in their entirety by reference. As disclosed in these patents, each of the memory cells 40 and 42 comprises a first terminal and second terminal with a channel therebetween. A floating gate (shown as 44 and 46, respectively for the cells 40 and 42) is formed over a portion of the channel and is insulated therefrom and is over a portion of the first terminal. The first terminals of memory cells 40 and 42 are connected to MOS transistors 48 and 50 respectively, which are in turn connected to the switching transistors 34 and 36. The gates of the transistors 48 and 50 are connected to the floating gates 44 and 46 respectively. Finally, the memory cells 40 and 42 further comprises control gates 52 and 54 respectively which overlap a portion of the channel. The control gates are connected together and receive the signal RCL. The second terminal of the memory cells 40 and 42 receive the signals BL and BL respectively.
In the operation of the circuit 10, the memory cells 40 and 42 are initially erased. As disclosed in U.S. Pat. Nos. 5,029,130 and 5,572,054, this means electrons are removed from the floating gates 44 and 46 respectively by tunneling electrons through an insulating layer to the control gates 52 and 54 respectively. This can be done, for example, by connecting the signal SL to ground, which connects the first terminals of the memory cells 40 and 42 to ground. The signal RCL is then connected to a source of high voltage such as +12 volts. This attracts the electrons on the floating gates 44 and 46 and causes them to tunnel through the insulating layer to the control gates 52 and 54, to be removed from the floating gates 44 and 46. The removal of the electrons from the floating gates 44 and 46 continues until the transistors 48 and 50 become conductive. This can be done by erasing the floating gates 44 and 46 so that the floating gates become positively charged.
Thereafter, one of the memory cells 40 or 42 is programmed. This can be accomplished by connecting the SL signal to +10 volts. WL is then connected to +1.8 volts. If memory cell 40 is to be programmed, then BL is connected to ground (or slightly above ground, such as 0.6 v) with BL connected to Vcc. Since the voltage on BL is higher than the voltage on WL, no electrons would flow in the channel between BL and SL. However, since BL is at ground (or 0.6 v), its electrons would flow from BL to SL and would be hot channel injected onto the floating gate 44, all as described in U.S. Pat. Nos. 5,029,130 and 5,572,054.
Once one of the memory cells 40 or 42 is programmed, then the state of the memory cells 40 and 42 can be written into the SRAM 20. This can be accomplished by connecting EERCL to Vcc volts thereby turning on the pass transistors 34 and 36 respectively. SL is then connected to 0.0 volts. If the memory cell 40 is programmed, then electrons on the floating gate 44 cause transistor 48 to block the signal from SL to pass through transistor 34 to the first node 30. However, for the memory cell 42, since the floating gate is erased, transistor 50 would conduct and therefore the voltage from SL is passed through the transistor 50 and through the pass transistor 36 to second node 32. Thus, the second node 32 is pulled down and the first node 30 is pulled up to Vcc, thereby programming the SRAM 20.
There are many drawbacks of the circuit 10. In particular, the circuit 10 does not permit the contents of the SRAM 20 to be written first and then written into the non-volatile memory cell. This leaves the disadvantage that programming has to occur always first into and from the non-volatile memory cells, which is time consuming.